The present invention relates to integrated circuit (IC) technology. More specifically, the present invention pertains to user-configurable interconnections among circuitry on different semiconductor chips in a multi-chip system.
Integrated circuits use a network of metal interconnects between individual semiconductor components, and are fabricated using a complicated process requiring a number of photolithographic masks extracted from the layout of the integrated circuits. The engineering cost of the layout and the fabrication cost of the photolithographic masks for a fully custom-designed integrated circuit is very high and can only be economically justified if the number of ICs to be produced is substantial. In addition, the production of such ICs with a fully customized design has a long delivery time. The development of user-programmable logic arrays, with programmable logic elements or modules, as illustrated in U.S. Pat. No. Re. 34,363 (Reissued) to Freeman, included herewith by reference, commonly known as Field Programmable Gate Arrays (FPGAs) has provided the user with an economical means to implement logic designs of relatively low complexity, with a short delivery time and with a reasonable performance. One measure of complexity of a logic design is the number of logic gates that is needed to implement that design.
These FPGAs roughly have a common architecture, consisting of an array of logic modules interspersed with a programmable interconnect architecture. The logic modules may or may not have programmability. The I/O pads may be programmed to be an input, an output, or a bidirectional I/O circuit for use in a bus. Different programming technologies, such as anti-fuses, non-volatile memory elements, memory element controlled switches, etc. may be used.
FPGAs are widely used in digital system design, for implementing many logic functions that otherwise would be implemented using a plurality of commercially available logic chips (so-called "glue-logic"). The use of FPGAs for prototyping and emulation of small integrated circuits under development has proven particularly useful to IC manufacturers. Time consuming computer simulations can be replaced by much faster emulations. Mistakes in an IC design may be found early on in the design process, saving both time and money.
However, due to the large overhead in die area for providing user-programmability, the maximum complexity IC-design that can be successfully implemented in a single FPGA is at least an order of magnitude smaller than the maximum complexity IC-design that can be implemented in a custom designed IC using the same semiconductor technology.
In order to implement, prototype or emulate very large logic designs, such as VLSI (Very Large Scale Integration) ICs, a plurality of FPGAs, possibly in combination with other, dedicated ICs such as memory chips, arithmetic units, processor units, etc. may be used, mounted together on a substrate (such as a PCB, a Printed Circuit Board; or an MCM, a Multi-Chip Module). The substrate provides routing between the bonding pads of the ICs. It is not economically feasible to produce customized routing substrates for every application. Instead, a fixed, well-chosen interconnect network must be present on the substrate, such that the same substrate with the ICs may be used successfully for many applications. We will refer to such a substrate with FPGAs and possibly other ICs on it as a "user-programmable multi-chip system".
The quality of a user-programmable multi-chip system may be expressed as a combination of two measures: the first measure is the performance at which an implemented design may be emulated, and the second measure is the area efficiency. The performance may roughly be calculated as the inverse of the maximum propagation delay along the critical path of an implementation. The area efficiency may be defined as the average number of logic gates implemented per unit area of the system, and may roughly be calculated as the product of a packaging technology-dependent factor and the "gate utilization". The "gate utilization" is a commonly used measure for FPGAs, and may be defined as the number of gates used towards implementing the logic design, divided by the total number of gates available on the FPGAs. The gate utilization is strongly dependent on the "flexibility" of the programmable routing architecture. The "flexibility" of a programmable routing architecture may be measured roughly as the number of programmable elements used in the programmable routing architecture.
U.S. Pat. No. 5,109,353 to M. D'Amour et al discloses an apparatus for emulation of electronic hardware systems using a plurality of FPGAs (Field Programmable Gate Arrays), richly interconnected through a fixed interconnect network and using a workstation for entering data and for programming the FPGAs. However, since this apparatus is directed to use with FPGAs that do not include the architecture of the present invention, it does not offer the merits of the present invention. More specifically, since in a multi-chip system the substrate only contains fixed interconnects, all flexibility of the inter-chip routing must be contained inside the integrated circuits, for example by providing fast, programmable interconnections among the I/O pads of the chips. The FPGAs used in this apparatus were not intended for use in a multi-chip system, and do not provide fast interconnections among a substantial number of their I/O pads.
In order to improve the performance of such an emulation apparatus, specialized routing chips may additionally be included in the array of integrated circuits mounted on the substrate. Such switching chips may consist of programmable switch networks such as programmable switch matrices or programmable multiplexers. Thus, the flexibility of the inter-chip routing is concentrated inside these switching chips. While this approach may increase the performance of the obtained multi-chip system, it does not offer the merits of compactness and modularity offered by the current invention.
U.S. Pat. No. 4,642,487 to W. Carter discloses a user-programmable special interconnect for a logic array. The architecture provides flexibility between the I/O pads and internal nodes through programmable junctions; and it also provides flexibility among the I/O pads. However, that architecture is not directed to providing fast, flexible interconnections among I/O pads, and due to a different architecture, it does not provide the performance offered by the present invention, since it requires signals to travel through at least two programmable junctions and at least one intermediate wire segment in order to go from one I/O pad to another.
U.S. Pat. No. 4,758,745 to A. Elgamal et al discloses a user-programmable integrated circuits interconnect architecture and test method. However, that architecture is directed to solving the routing problem among modules on one integrated circuit and does not address the interconnection among I/O pads.
U.S. Pat. No. 5,107,146 to K. A. El-Ayat discloses a mixed mode analog/digital programmable interconnection architecture. The architecture provides flexibility between the I/O pads and the circuitry on the integrated circuit and also among some of the I/O pads. However, that architecture is not directed to providing fast, flexible interconnections among I/O pads, and due to a different interconnection architecture, it does not offer the performance and flexibility offered by the present invention.
U.S. Pat. No. 5,162,893 to Y. Okano et al discloses a semiconductor integrated circuit device with an enlarged internal logic circuit area, obtained by adding specific peripheral circuits. However, that architecture is directed to providing additional area for logic and does not provide flexible interconnections among bonding pads or between bonding pads and the nodes of the main circuitry.
U.S. Pat. No. 5,066,831 to R. K. Spielberger et al discloses a universal semiconductor chip package having programmable pads located on a surface of the package. However, that approach is directed to providing programmable connections between the pads of an integrated circuit and the pins of its package. Moreover, it does not integrate the programmable circuits on the same integrated circuit as the main circuitry, as is the case in the present invention.
Whatever the precise merits, features and advantages of the above cited references and approaches, none of them achieves or fulfills the purposes of the user-programmable inter-chip interconnect architecture of the present invention.
The present invention also pertains to multi-processors. A multi-processor is a computation apparatus that includes a plurality of processor units. These processor units may be mounted on a substrate, together with other integrated circuits such as memory, arithmetic units, etc. It is known in the art that it is advantageous to have fast, programmable interconnections between these processor units. The programmable inter-chip interconnection architecture of the current invention may be used with such:processor units and possibly with other integrated circuits.
The present invention also pertains to digital signal multi-processors. One application of digital signal processors is to encode and decode data in order to reliably and efficiently store or transmit it. Depending on the data type and the type of storage or the type of transmission channel, different encoder and decoder algorithms exist. Such algorithms all share logic blocks such as multipliers and discrete cosine transform units, etc. as known in the art. The programmable interchip interconnection architecture of the current invention may be used with such blocks so that a plurality of encoding and decoding algorithms and other algorithms may be performed.